1. Field of the Invention
The invention relates in general to an image processing technique, and more particularly, to a technique for reducing a decoding time and optimizing an image processing efficiency.
2. Description of the Related Art
Persistently expanding sizes of image displays is one of the development trends of a current multimedia display system, and so it is necessary that an operating speed of an image processing apparatus be correspondingly increased. Taking a High-Definition Television (HDTV) monitor as an example, a decoding device in the HDTV monitor needs to process at least 60 1920*1080 frames per second. Therefore, solutions for reducing a cycle and enhancing a decoding efficiency of a decoding device are now much sought for.
A Boolean entropy decoder prevalently implemented as a decoder in an image processing system is for converting a bitstream to a boolean value corresponding to image data. FIG. 1 shows a block diagram of a stereotypic Boolean decoder. In the structure shown, a decoder 100 sequentially generates two boolean values within every cycle T. When generating a boolean value B0, a split S0 corresponding to the boolean value B0 is first calculated according to an equation below:
                              S          0                =                  1          +                                                    (                                  R                  -                  1                                )                            *                              P                0                                      256                                              Equation        ⁢                                  ⁢                  (          1          )                    
A range R0 and a value V0 corresponding to the boolean value B0 are associated with a previous boolean value and may be obtained in advance; a probability P0 is obtained from a look-up table. A circuit combination 12A performs operations of Equation (1) to provide the split S0. In practice, the range R0, the split S0 and the value V0 are all integers represented in binary eight bits. The value V0 of an entire frame is usually placed at first eight bits of a bitstream.
A comparator 12B compares the split S0 and the value V0 to determine whether the boolean value B0 is 1 or 0. The boolean value B0 is 1 when the split S0 is smaller than or equals to the value V0, or else is 0 when the split S0 is greater than the value V0.
A range R1 and a value V1 corresponding to the next boolean value B1 are associated with the boolean value B0, and are generated via a renormalization procedure after the boolean value B0 is determined. When the boolean value B0 is 1, an initial value R1(0) of R1 is R0 subtracted by S0 and an initial value V1(0) of V1 is V0 subtracted by S0. When the boolean value B0 is 0, the initial value R1(0) of R1 equals S0 and the initial value V1(0) of V1 equals V0. As shown in FIG. 1, a subtractor 12C is for generating a difference between the range R0 and the split S0. The boolean value B0 is provided to a multiplexer 12D for determining whether the initial value R1(0) provided to a renormalizing unit 12E is the split S0 or the difference between the range R0 and the split S0. Similarly, the boolean value B0 is also provided to a multiplexer 12F for controlling whether the initial value V1(0) provided to a renormalizing unit 12E is the value V0 or the difference between the value V0 and the split S0.
The renormalizing unit 12E then selectively adjusts and confirms the range R1 and the value V1. The approach for the adjustment is represented below as:while (R1<128){R1=R1*2;V1=[(V1*2)+nbit(1)]}  Equation (2)
That is to say, R1 is multiplied by 2 when a current R1 is smaller than 128 until R1 becomes greater than or equal to 128. Each time the range R1 is increased, the value V1 is also correspondingly multiplied by 2 and then added with a first bit of an unused part in the bitstream. Taking R1 becoming greater than 128 after it is multiplied by two for three times as an example, the renormalizing unit 12E fetches first three bits in an unused part in the bitstream to generate the value V1. As shown in FIG. 1, a value N1 represents a number of bits that the renormalizing unit 12E needs to fetch from an unused part of the bitstream to generate the value V1; a value N2 represents a number of bits that a renormalizing unit 14E needs to fetch from an unused part of the bitstream to generate the value V2. A buffer 18 in FIG. 1 temporarily stores an unused segment of the bitstream, which is to be utilized by the renormalizing units 12E and 14E to generate the value V1. That is, when the renormalizing units 12E and 14E respectively generate the values V1 and V2, it is necessary that the buffer 18 be provided with predetermined bits required by operations of the renormalizing units 12E and 14E.
After having confirmed the range R1 and the value V1, a combinational circuit 14A calculates the split S1 according to the range R1, a probability P1 (may be obtained through a look-up table) and Equation (1). By comparing the split S1 and the value V1 generated by the renormalizing unit 12E, a comparator 14B determines whether the boolean value B1 is 1 or 0.
Likewise, a range R2 and a value V2 corresponding to the next boolean value B2 are associated with the boolean value B1, and are generated via a renormalization procedure after the boolean value B1 is determined. As shown FIG. 1, a subtractor 14C is for generating a difference between the range R1 and the split S1. The boolean value B1 is provided to the multiplexer 14D, and is utilized for determining whether an initial value R2(0) of R2 provided to the renormalizing unit 14E is the split S1 or the difference between the range R1 and the split S1. The boolean value B1 is also provided to the multiplexer 14E, and is utilized for determining whether an initial value V2(0) of V2 provided to the renormalizing unit 14E equals to the value V1 or the difference between the value V1 and the split S1. The renormalizing unit 14E then determines the range R2 and the value V2 of the next boolean value B2.
In practice, the circuits 12A to 12E may be utilized to generate the boolean value B2 and the circuits 14A to 14E may be utilized to generate a subsequent boolean value B3—the cycle is repetitively performed to sequentially generate a series of boolean values.
As shown in FIG. 1, an updating unit 16 respectively receives the value N1 from the renormalizing unit 12E and the value N2 from the renormalizing unit 14E. The value N1 represents the number of bits that the renormalizing unit 12E needs to fetch from an unused part of the bitstream to generate the value V2. The value N2 represents the number of bits that a renormalizing unit 14E needs to fetch from an unused part of the bitstream to generate the value V2. According to the values N1 and N2, the updating unit 16 calculates the total number of bits used in the current cycle to update a content of the buffer 18.
FIG. 2 shows an example of a content of the buffer 18. Assume that the buffer 18 has a storage capacity of 16 bits and stores bits [20:35] (i.e. from the 20th bit to the 35th bit) of the bitstream during a first period T1. For example, when a sum of the values N1 and N2 is 8, it means that the first 8 bits [20:27] among the bits [20:35] have been used by the renormalizing units 12E and 14E during the cycle T1. Therefore, the updating unit 16 demands a memory (not shown) of the bitstream and fetches the subsequent 8 bits [36:43] in the bitstream, and updates the content of the buffer 18 to the bits [28:43] before a second cycle T2 starts. That is, the first 8 bits that have already been used are deleted, and the 16 bits that are not yet used are updated into the content of the buffer 18, so as to offer the updated content to the renormalizing units 12E and 14E to generate values V3 and V4 in the second cycle T2. Similarly, the updating unit 16 updates the buffer 18 before a next cycle T3 starts according to the number (the total of the values N3 and N4) of bits that are used in the generation of the values V3 and V4.
Each time in the renormalization procedure, upmost 7 bits are fetched from the bitstream to generate one value V. The capacity of the buffer 18 is generally designed to be sufficient for generating the values V corresponding to two boolean values in a single operating cycle. Referring to FIG. 2, the Boolean entropy decoder 100 generates two boolean values in each cycle, and the content of the buffer 18 varies or remains unchanged along with different numbers of bits consumed in the cycles.
With respect to the structure in FIG. 1, the value N1 must be generated before the value N2, and the updating unit 18 can only determine the number of bits to be fetched to update the content of the buffer 18 after the renormalizing unit 14E generates the value N2. Taking FIG. 2 as an example, the renormalizing unit 14E generates the value N2 at a time point tA1, and the updating unit 16 fetches needed bits from the bitstream for updating the buffer 18 during the remaining time period from the time point tA1 to the end of the cycle T1. That is to say, only after the content of the buffer 18 is completely updated, does the next cycle T2 begin. Therefore, it is observed that the time spent for fetching data and updating the buffer prolongs the cycles of the Boolean entropy decoder 100, such that a corresponding operating frequency is lowered to even lead to a failure of the Boolean entropy decoder 100 in meeting requirements of certain high definition video systems.